High dielectric constant materials : VLSI MOSFET applications / edited by Howard Huff and D.C. Gilmer.

Contributor(s): Huff, Howard | Gilmer, D. C. (David C.).

Material type: materialTypeLabel

BookSeries: Springer series in advanced microelectronics ; 1437-0387.Publisher: New York, NY : Springer-Verlag Berlin Heidelberg, 2005Description: xxiv, 710 p. :/bill. ; 25 cm. + hbk.ISBN: 3540210814.Subject(s): Microelectronics

| Integrated circuits -- Very large scale integration

| Metal oxide semiconductor field-effect transistors

| Dielectrics

DDC classification: 621.3815284

Contents:

The economic implications of Moore's law / G. D. Hutcheson -- Part I: Classical regime for SiO2 -- Brief notes on the history of gate dielectrics in MOS devices / E. Kooi, A. Schmitz -- SiO2 based MOSFETS: Film growth and Si-SiO2 interface properties / E. A. Irene -- Oxide reliability issues / R. Degraeve -- Part II: Transition to silicon oxynitrides -- Gate dielectric scaling to 2.0-1.0nm: SiO2 and silicon oxynitride / S. -H. Lo and Y. Taur -- Optimal scaling methodologies and transistor performances / T. Skotnicki, F. Boeuf -- Silicon oxynitride gate dielectric for reducing gate leakage and boron penetration prior to high-k gate dielectric implementation / H. -H. Tseng -- Part III: Transition to high-k gate dielectrics -- Alternative dielectrics for silicon-based transistors: selection via multiple criteria / J. -P. Maria -- Materials issues for high-k gate dielectric selection and integration / R. M. Wallace, G. D. Wilk -- Designing interface composition and structure in high dielectric constant gate stacks / G. N. Parsons -- Electronic structure of alternative high-k dielectrics / G. Lucovsky, J. L. Whitten -- Physicochemical properties of selected 4d, 5d and rare earth metals in silicon / A. A. Istratov, E. R. Weber -- High-k gate dielectric deposition technologies / J. P. Chang -- Issues in metal gate electrode selection for bulk CMOS devices / V. Misra -- CMOS IC fabrication issues for high-k gate dielectric and alternate electrode materials / L. Colombo, A. L. P. Rotondaro, M. R. Visokay, J. J. Chambers -- Characterization and metrology of medium dielectric constant gate dielectric films / A. C. Diebold, W. W. Chism -- Electrical measurement issues for alternative gate stack systems / G. A. Brown -- High-k gate dielectric materials integrated circuit device design issues / Y. -Y. Fan, S. P. Mudanai, W. Chen, L. F. Register, S. K. Banerjee -- Part IV: Future directions for ultimate scaling technology generations -- High-k crystalline gate dielectrics: a research perpective / F. J. Walker, R. A. McKee -- High-k crystalline gate dielectrics: an IC manufacturer's perspective / R. Droopad, K. Eisenbeiser, A. A. Demkov -- Advanced MOS-devices / J. Boker, T. -J. King, J. Hergenrother, J. Bude, D. Muller, T. Skotnicki, S. Monfray, G. Timp.

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Enhanced descriptions from Syndetics:

Issues relating to the high-K gate dielectric are among the greatest challenges for the evolving International Technology Roadmap for Semiconductors (ITRS). More than just an historical overview, this book will assess previous and present approaches related to scaling the gate dielectric and their impact, along with the creative directions and forthcoming challenges that will define the future of gate dielectric scaling technology. Topics include: an extensive review of Moore's Law, the classical regime for SiO2 gate dielectrics; the transition to silicon oxynitride gate dielectrics; the transition to high-K gate dielectrics (including the drive towards equivalent oxide thickness in the single-digit nanometer regime); and future directions and issues for ultimate technology generation scaling. The vision, wisdom, and experience of the team of authors will make this book a timely, relevant, and interesting, resource focusing on fundamentals of the 45 nm Technology Generation and beyond.

Includes bibliographical references and index.

Table of contents provided by Syndetics

1 The Economic Implications of Moore's Law (p. 1)
1.1 Introduction (p. 1)
1.2 Moore's Law: A Description (p. 1)
1.3 The History of Moore's Law (p. 2)
1.4 The Microeconomics of Moore's Law (p. 13)
1.5 The Macroeconomics of Moore's Law (p. 21)
1.6 Moore's Law Meets Moore's Wall: What is Likely to Happen (p. 23)
1.7 Conclusion (p. 27)
1.8 Appendix A (p. 28)
References (p. 30)
Part I Classical Regime for SiO 2
2 Brief Notes on the History of Gate Dielectrics in MOS Devices (p. 33)
2.1 Early Attempts to Make Insulating-Gate Field-Effect Transistors; Surface States (p. 33)
2.2 Passivation of Silicon Surfaces by Thermal Oxidation; Planar Transistor Technology (p. 34)
2.3 Positive Oxide Charge and Surface States at the Si-SiO 2 Interface (p. 35)
2.4 Instabilities Due to Ion Drift Effects (p. 36)
2.5 Phosphate-silicate Glass Helped (p. 37)
2.6 Other Materials Tried as Gate-Dielectric Layers (p. 37)
2.7 Thermal Oxidation of Silicon (p. 38)
2.8 Segregation of Dopants at the Si-SiO 2 Interface (p. 39)
2.9 Other Silicon Oxide Preparation Techniques (p. 40)
2.10 Thick Field Oxides (p. 41)
2.11 Breakdown Strength of SiO 2 , Defect Density, Moore's Law (p. 41)
2.12 Weak Oxide Regions in MOS Structures, Kooi Effect (p. 41)
2.13 Al Gate MOS Devices; PMOS IC's (p. 42)
2.14 Silicon Gate MOS Devices, NMOS and CMOS IC's (p. 42)
2.15 Decrease of Oxide Thickness Connected with Downscaling of MOS Structure (p. 43)
References (p. 43)
3 SiO 2 Based MOSFETS: Film Growth and Si-SiO Interface Properties (p. 45)
3.1 SiO 2 Prior to 1970 (p. 45)
3.1.1 Introduction (p. 45)
3.1.2 A Brief Historical Survey (p. 45)
3.1.3 What Is a MOSFET? (p. 46)
3.1.4 How Does a MOSFET Work? (p. 48)
3.1.5 Interface Electronic States and Charge (p. 48)
3.1.6 Implications of the Charges on MOSFET Operation (p. 49)
3.1.7 The Silicon Oxidation Model: Early Studies (p. 51)
3.2 After 1970: Progress in Understanding (p. 55)
3.2.1 In situ Real-Time Oxidation Studies: Dry O 2 , the Effects of Water and Other Impurities (p. 56)
3.2.2 Arrhenius Behavior and Deviations (p. 61)
3.2.3 Stress Effects on Oxidation Kinetics (p. 62)
3.2.4 Orientation Effects on Oxidation Kinetics (p. 65)
3.2.5 Effects of Light on Oxidation Kinetics (p. 68)
3.2.6 The Thin Film Regime ( (p. 71)
3.2.7 The Si-SiO 2 Interface: Measurement and Implications (p. 73)
3.3 Modern Era: The Quest for Thinner SiO 2 and Alternatives (p. 76)
3.3.1 Ultra-thin SiO 2 Film Metrology (p. 76)
3.3.2 Interfacial Roughness at the Si-SiO 2 Interface (p. 80)
3.3.3 Ultra-thin Film SiO 2 Films and the Future of Gate Dielectrics (p. 85)
References (p. 86)
4 Oxide Reliability Issues (p. 91)
4.1 Thin Oxide Layer Degradation Under Electrical Stress (p. 91)
4.1.1 Interface Trap Creation (p. 92)
4.1.2 Oxide Charge Trapping (p. 92)
4.1.3 Hole Fluence (p. 93)
4.1.4 Neutral Electron Trap Generation (p. 96)
4.1.5 Stress-Induced Leakage Current (p. 97)
4.1.6 Trap Generation Mechanism: Discussion (p. 100)
4.2 Oxide Breakdown (p. 102)
4.2.1 Breakdown Modeling (p. 102)
4.2.2 Soft Breakdown (p. 105)
4.3 Breakdown Acceleration Models (p. 107)
4.3.1 Voltage or Field Extrapolation (p. 108)
4.3.2 Temperature Dependence of Breakdown (p. 110)
4.3.3 Oxide Reliability Predictions (p. 111)
4.4 Conclusion (p. 111)
References (p. 111)
Part II Transition to Silicon Oxynitrides
5 Gate Dielectric Scaling to 2.0-1.0 nm: SiO 2 and Silicon Oxynitride (p. 123)
5.1 Device Requirements on Gate Dielectric Scaling (p. 123)
5.2 Definition of Gate Dielectric Thickness (p. 127)
5.2.1 Electron Distribution in Accumulation and Inversion Layers (p. 127)
5.2.2 Polysilicon Gate Depletion Effect (p. 127)
5.2.3 Gate Capacitance and Equivalent Oxide Thickness (EOT) Determination (p. 130)
5.3 Tunneling Current of SiO 2 (p. 132)
5.3.1 Modeling Electron Tunneling from Quasi-bound States (p. 133)
5.3.2 Tunneling Current as a Function of Thickness (p. 133)
5.4 Tunneling Currents of Silicon Oxynitride (p. 135)
5.5 Application Dependence of Gate Dielectric Limit (p. 137)
References (p. 140)
6 Optimal Scaling Methodologies and Transistor Performance (p. 143)
6.1 Introduction (p. 143)
6.2 Scaling and Device Physics (p. 145)
6.2.1 MASTAR Model (p. 145)
6.2.2 Voltage-Doping Transformation (p. 148)
6.2.3 Short Channel Effect (SCE) (p. 150)
6.2.4 Drain-Induced Barrier Lowering (DIBL) (p. 151)
6.2.5 Junction Depth Effect (p. 151)
6.2.6 Understanding the """"Good Design Rules"""" (p. 153)
6.3 Limitations of Conventional Scaling (p. 154)
6.3.1 Limitations Menacing the V th /V dd Scaling (p. 154)
6.3.2 Limitations Menacing the T ox_e /L Scaling (p. 155)
6.3.3 Limitations Menacing the X j /L Scaling (p. 161)
6.3.4 Limitations Menacing the T dep /L Scaling (p. 163)
6.3.5 Impact on the Roadmap (p. 163)
6.4 Extending Validity of Moore's Law (p. 165)
6.4.1 Strategies Based on Increased Gate Drive (V dd -V th ) (p. 165)
6.4.2 Strategies Based on Even More Aggressive Scaling (p. 169)
6.4.3 Strategies Based on New Materials (p. 176)
6.4.4 Strategies Based on Improvements of Device Architecture (p. 182)
6.4.5 How Far Can We Go and How Much Should We Pay? (p. 187)
6.5 Conclusions (p. 190)
References (p. 192)
7 Silicon Oxynitride Gate Dielectric for Reducing Gate Leakage and Boron Penetration Prior to High-k Gate Dielectric Implementation (p. 195)
7.1 Introduction (p. 195)
7.2 Integrated RTCVD Oxynitride(ION) Process (p. 197)
7.2.1 Experiment (p. 197)
7.2.2 Results and Discussion (p. 198)
7.3 JVD Nitride (p. 207)
7.3.1 Experiment (p. 207)
7.3.2 Results and Discussion (p. 207)
7.4 DPN Oxynitride (p. 211)
7.4.1 Experiment (p. 211)
7.4.2 Results and Discussion (p. 212)
7.5 Conclusion (p. 218)
References (p. 219)
Part III Transition to High-k Gate Dielectrics
8 Alternative Dielectrics for Silicon-Based Transistors: Selection Via Multiple Criteria (p. 223)
8.1 Introduction (p. 223)
8.2 Discussion (p. 226)
8.2.1 Development of Selection Criteria (p. 226)
8.2.2 Application of the Selection Criteria (p. 239)
8.3 Conclusions (p. 247)
References (p. 248)
9 Materials Issues for High-k Gate Dielectric Selection and Integration (p. 253)
9.1 Introduction (p. 253)
9.1.1 Improved Performance Through Scaling (p. 254)
9.1.2 Leakage Current and Power (p. 256)
9.2 MIS (Metal-Insulator-Semiconductor) Structures (p. 257)
9.2.1 Issues for Interface Engineering (p. 257)
9.2.2 High-k Device Modeling and Transport (p. 260)
9.3 Materials Properties and Integration Considerations (p. 261)
9.3.1 Permittivity and Barrier Height (p. 261)
9.3.2 Thermodynamic Stability on Si (p. 266)
9.3.3 Interface Quality (p. 269)
9.3.4 Film Morphology (p. 270)
9.3.5 Gate Compatibility (p. 272)
9.3.6 Process Compatibility (p. 275)
9.3.7 Reliability (p. 276)
9.4 Conclusions (p. 277)
References (p. 277)
10 Designing Interface Composition and Structure in High Dielectric Constant Gate Stacks (p. 287)
10.1 Introduction (p. 287)
10.2 Thermodynamic Stability of Dielectrics on Silicon (p. 290)
10.2.1 Silicide Formation and SiO Evolution During Post-deposition Processing (p. 290)
10.2.2 Affect of Excess Oxygen on Final State Energetics (p. 292)
10.2.3 Chemical Mechanisms in Silicon Interface Oxidation (p. 295)
10.3 Kinetic Rate Processes During Metal Oxide Deposition (p. 297)
10.3.1 Driving Forces for Reactions During Metal Oxide Deposition on Clean Silicon (p. 297)
10.3.2 Role of Surface Pre-treatment and Passivation (p. 300)
10.3.3 Important Issues (p. 303)
10.4 Gate Electrode/Dielectric Interfaces (p. 304)
10.4.1 Polysilicon/Dielectric Interfaces (p. 304)
10.4.2 Metal/Dielectric Interfaces (p. 304)
10.5 Conclusion (p. 305)
References (p. 306)
11 Electronic Structure of Alternative High-k Dielectrics (p. 311)
11.1 Introduction (p. 311)
11.2 SiO 2 and the Si-SiO 2 Interface (p. 313)
11.2.1 Interfacial Transition Regions Between Crystalline Si and Non-crystalline SiO 2 (p. 313)
11.2.2 Local Atomic Structure of SiO 2 (p. 315)
11.2.3 Electronic Structure of SiO 2 (p. 316)
11.2.4 Local Atomic Structure of the Si-SiO 2 Interface (p. 319)
11.3 Alternative Dielectrics (p. 322)
11.3.1 Classification of High-K Non-crystalline Dielectrics (p. 322)
11.4 Electronic Structure of Transition Metal Dielectrics (p. 327)
11.4.1 Empirical Correlations Between Electronic Structure and Atomic d-State Energies (p. 327)
11.4.2 Extension of Ab Initio Calculations to Transition Metal Oxides (p. 330)
11.5 Experimental Studies of Electronic Structure (p. 333)
11.5.1 Valence Band (p. 333)
11.5.2 Anti-bonding Conduction Band States of TM Oxides (p. 333)
11.5.3 TM and RE Alloys (p. 335)
11.5.4 XPS and AES Results for Zr Silicates (p. 339)
11.5.5 Trapping at Transition Metal Atoms in Al 2 O 3 -Ta 2 O 5 Alloys (p. 347)
11.6 Interface Electronic Structure Applied to Direct Tunneling in Silicate Alloys (p. 348)
11.7 Conclusion (p. 353)
References (p. 355)
12 Physicochemical Properties of Selected 4d, 5d, and Rare Earth Metals in Silicon (p. 359)
12.1 Introduction (p. 359)
12.2 Crystal Lattice Site of 4d, 5d, and Rare Earth Metals in Silicon (p. 360)
12.3 Solubility of 4d, 5d, and Rare Earth Metals in Silicon (p. 361)
12.4 Diffusivity of 4d, 5d, and Rare Earth Elements in Silicon (p. 362)
12.4.1 Diffusivity of Pr, Sr, Ba, Zr, and Hf (p. 362)
12.4.2 Diffusivity of Er, Pm, Yb, Tb, Ho, and Mo in Silicon . (p. 364)
12.4.3 Diffusivity of Heavy Metals in Silicon: A Discussion (p. 367)
12.5 Energy Levels in the Band Gap (p. 368)
12.5.1 Energy Levels of Y, Zr, and Hf (p. 368)
12.5.2 Electrical Levels of Mo, Nb, Ta, and W (p. 369)
12.5.3 Electrical Levels of the Rare Earth Elements: Er, Tb, Ho, or Dy (p. 370)
12.6 Effect of 4d, 5d, and Rare Earth Metals on Minority Carrier Recombination Lifetime and Device Performance (p. 372)
12.7 Summarizing Discussion (p. 374)
References (p. 375)
13 High-k Gate Dielectric Deposition Technologies (p. 379)
13.1 Atomic Layer Deposition (p. 380)
13.1.1 Technology Description (p. 380)
13.1.2 Chemical Reaction Mechanisms and Precursors (p. 381)
13.1.3 Processing Reactors and Chemical Delivery System (p. 387)
13.1.4 Film Composition, Microstructure, and Electrical Results (p. 391)
13.2 Chemical Vapor Deposition (p. 391)
13.2.1 Technology Description (p. 391)
13.2.2 Chemical Reaction Mechanisms and Kinetics (p. 392)
13.2.3 Processing Reactors and Chemical Delivery System (p. 392)
13.2.4 Film Composition, Microstructure, and Electrical Results (p. 393)
13.3 Plasma-Enhanced Atomic Layer Deposition (p. 393)
13.3.1 Technology Description (p. 393)
13.3.2 Chemical Reaction Mechanisms and Kinetics (p. 394)
13.3.3 Processing Reactors and Chemical Delivery System (p. 395)
13.3.4 Film Composition, Microstructure, and Electrical Results (p. 396)
13.4 Plasma Enhanced Chemical Vapor Deposition (p. 396)
13.4.1 Technology Description (p. 396)
13.4.2 Chemical Reaction Mechanisms and Kinetics (p. 397)
13.4.3 Processing Reactors and Chemical Delivery System (p. 397)
13.4.4 Film Composition, Microstructure, and Electrical Results (p. 399)
13.5 Physical Vapor Deposition (p. 399)
13.5.1 Technology Description (p. 399)
13.5.2 Chemical Reaction Mechanisms and Kinetics (p. 400)
13.5.3 Processing Reactors and Chemical Delivery System (p. 401)
13.5.4 Film Composition, Microstructure, and Electrical Results (p. 401)
13.6 Molecular Beam Epitaxy (p. 403)
13.6.1 Technology Description (p. 403)
13.6.2 Chemical Reaction Mechanisms and Kinetics (p. 403)
13.6.3 Processing Reactors and Chemical Delivery System (p. 404)
13.6.4 Film Composition, Microstructure, and Electrical Results (p. 404)
13.7 Ion Beam Assisted Deposition (p. 404)
13.7.1 Technology Description (p. 404)
13.7.2 Chemical Reaction Mechanisms and Kinetics (p. 404)
13.7.3 Processing Reactors and Chemical Delivery System (p. 405)
13.7.4 Film Composition, Microstructure, and Electrical Results (p. 405)
13.8 Sol-gel Deposition (p. 405)
13.8.1 Technology Description (p. 405)
13.8.2 Chemical Reaction Mechanisms and Kinetics (p. 406)
13.8.3 Processing Reactors and Chemical Delivery System (p. 406)
13.8.4 Film Composition, Microstructure, and Electrical Results (p. 406)
13.9 Summary (p. 406)
References (p. 407)
14 Issues in Metal Gate Electrode Selection for Bulk CMOS Devices (p. 415)
14.1 Background (p. 415)
14.2 Metal Gate Selection Criteria (p. 416)
14.3 Other Challenges with Metal Gates (p. 418)
14.4 Metal Gate Candidates for NMOS Devices (p. 419)
14.4.1 Metal Nitrides (p. 419)
14.4.2 Metal Silicon Nitrides (p. 423)
14.4.3 Binary Metal Alloys (p. 425)
14.5 Metal Candidates for PMOS Devices (p. 430)
14.6 Metals on High-k Dielectrics (p. 430)
14.7 Conclusion (p. 431)
References (p. 432)
15 CMOS IC Fabrication Issues for High-k Gate Dielectric and Alternate Electrode Materials (p. 435)
15.1 Introduction (p. 435)
15.2 The """"Standard"""" CMOS Flow (p. 436)
15.2.1 Isolation (p. 436)
15.2.2 Well and Channel Doping (p. 438)
15.2.3 Gate Dielectric/Gate Stack (p. 438)
15.2.4 Source and Drain (p. 440)
15.2.5 Silicide and Contact (p. 440)
15.3 Insertion of High-k Gate Dielectric into the CMOS Flow (p. 442)
15.3.1 High-k Materials as a Substitute for SiON (p. 442)
15.3.2 Interactions with/During the Gate Electrode Deposition (p. 444)
15.3.3 Gate Electrode Etch Concerns - Stopping on High-k (p. 445)
15.3.4 Surface Preparation (Cleans) in the Presence of High-k Materials (p. 445)
15.3.5 Poly Silicon Oxidation (p. 445)
15.3.6 Source and Drain Extension Formation (p. 446)
15.3.7 Spacer Formation (p. 446)
15.3.8 Source and Drain Formation (p. 447)
15.3.9 Silicidation (p. 448)
15.3.10 Contact and Metallization - Low Temperature Processes (p. 448)
15.3.11 Sinter (p. 448)
15.4 Alternative Electrode Materials (p. 449)
15.4.1 The Need for Alternative Electrode Materials (p. 449)
15.4.2 Material Classes Under Consideration as Alternative Electrode Materials (p. 450)
15.4.3 Dual Work Function Gate Stack Implementation (p. 457)
15.5 Integration of High-k Gate Dielectrics and Metal Gates into Advanced Devices (p. 461)
15.5.1 Advanced Planar Integration Schemes (p. 461)
15.5.2 Advanced Non-planar Integration Schemes (p. 466)
15.6 Conclusions (p. 470)
References (p. 471)
16 Characterization and Metrology of Medium Dielectric Constant Gate Dielectric Films (p. 483)
16.1 Introduction (p. 483)
16.2 Structural and Chemical Characterization of Medium ¿ Film Stacks (p. 486)
16.2.1 Characterization Methods (p. 487)
16.2.2 Structure/Function Relationships (p. 500)
16.2.3 Characterization Results for Medium k (p. 501)
16.3 Optical Models for Medium k Films (p. 503)
References (p. 517)
17 Electrical Measurement Issues for Alternative Gate Stack Systems (p. 521)
17.1 Introduction (p. 521)
17.2 Capacitance-Voltage Measurement (p. 522)
17.2.1 Overview (p. 522)
17.2.2 Background (p. 523)
17.2.3 Definition of Capacitance (p. 524)
17.2.4 Measurement of Capacitance and Its Output in Series or Parallel Mode (p. 528)
17.2.5 More Complex Equivalent Circuits (p. 531)
17.2.6 Additional Capacitance-Related Measurement Topics for High-k Gate Stacks (p. 537)
17.2.7 Practical Capacitance Measurement Issues (p. 544)
17.3 Analysis of Device/Material Parameters from Established C-V Data (p. 548)
17.4 Current-Voltage Measurement (p. 551)
17.4.1 Parasitic Series Resistance (p. 551)
17.4.2 Temperature Dependence (p. 553)
17.4.3 Time Dependence Effects (p. 553)
17.5 Determination of DC Conduction Mechanisms (p. 556)
17.6 Sample Design and Preparation Issues (p. 560)
17.7 Conclusion (p. 562)
References (p. 562)
18 High-k Gate Dielectric Materials Integrated Circuit Device Design Issues (p. 567)
18.1 Introduction (p. 567)
18.2 Fundamental Issues on Gate Capacitance and Current Modeling (p. 568)
18.2.1 Models (p. 568)
18.2.2 ZrO 2 and HfO 2 NMOSCAP C g , I g -V g Analysis (p. 574)
18.2.3 Conclusions for Fundamental Issues on Gate Capacitance and Current Modeling (p. 579)
18.3 Wave Function Penetration Effect Issues (p. 579)
18.3.1 Quantum Transmitting Boundary (QTBM) Method (p. 580)
18.3.2 Effects on Quantization (p. 583)
18.3.3 High-k Tunneling Gate Currents Trend Study (p. 584)
18.3.4 Wave Function Penetration Effects on Gate Capacitance (p. 586)
18.4 Maxwell-Wagner Effects and Power Law Dispersion (p. 591)
18.4.1 Interfacial Polarization in High-k Gate Stacks (p. 591)
18.4.2 Power Law Dispersion and Its Impact on Device Performance (p. 597)
18.4.3 Conclusions for Maxwell-Wagner Effects and Power Law Dispersion (p. 602)
18.5 Conclusions (p. 602)
References (p. 603)
Part IV Future Directions for Ultimate Scaling Technology Generations
19 High-k Crystalline Gate Dielectrics: A Research Perspective (p. 607)
19.1 Introduction (p. 607)
19.2 The Path to the Perovskites and COS (p. 610)
19.2.1 MBE (p. 610)
19.2.2 Rules for COS (p. 612)
19.3 The Material System of COS (p. 614)
19.3.1 Alkaline Earth Metal Silicide (p. 615)
19.3.2 Alkaline Earth Oxides (p. 616)
19.3.3 Perovskites (p. 617)
19.4 The Implementation of COS (p. 619)
19.4.1 Layer-Sequenced COS Growth (p. 619)
19.4.2 The Importance of the Silicide (p. 625)
19.4.3 Alkaline Earth Metal (p. 628)
19.4.4 Oxide Growth (p. 628)
19.5 Electrical Properties (p. 629)
19.5.1 Band Offset (p. 630)
19.5.2 Interface Traps (p. 631)
19.5.3 Channel Mobility (p. 633)
19.6 Conclusion (p. 634)
References (p. 635)
20 High-k Crystalline Gate Dielectrics: An IC Manufacturer's Perspective (p. 639)
20.1 Introduction (p. 639)
20.2 Theoretical Overview (p. 644)
20.3 Perovskite Surface (p. 644)
20.4 Oxide Deposition (p. 647)
20.5 Growth Template (p. 648)
20.6 Substrate Preparation (p. 649)
20.7 Initial Nucleation (p. 650)
20.8 Stability of the Interface (p. 653)
20.9 Structural Properties (p. 654)
20.10 Band Discontinuity (p. 658)
20.11 Device Results (p. 661)
20.12 Conclusion (p. 663)
References (p. 664)
21 Advanced MOS-Devices (p. 667)
21.1 Introduction (p. 667)
21.1.1 Prospectus (p. 672)
21.2 The Ballistic Nanotransitor (p. 674)
21.3 Vertical Replacement Gate MOSFET (p. 681)
21.4 The Double-Gate FinFET (p. 688)
21.5 Silicon-On-Nothing MOSFETs (p. 692)
21.6 Conclusion (p. 701)
References (p. 702)
Index (p. 707)