Enhanced descriptions from Syndetics:

PRINCIPLES OF MODERN DIGITAL DESIGN

FROM UNDERLYING PRINCIPLES TO IMPLEMENTATION--A THOROUGH INTRODUCTION TO DIGITAL LOGIC DESIGN

With this book, readers discover the connection between logic design principles and theory and the logic design and optimization techniques used in practice. Therefore, they not only learn how to implement current design techniques, but also how these techniques were developed and why they work. With a deeper understanding of the underlying principles, readers become better problem-solvers when faced with new and difficult digital design challenges.

Principles of Modern Digital Design begins with an examination of number systems and binary code followed by the fundamental concepts of digital logic. Next, readers advance to combinational logic design. Armed with this foundation, they are then introduced to VHDL, a powerful language used to describe the function of digital circuits and systems.

All the major topics needed for a thorough understanding of modern digital design are presented, including:

VHDL-based logic design examples are provided throughout the book to illustrate both the underlying principles and practical design applications. Each chapter is followed by exercises that enable readers to put their skills into practice by solving realistic digital design problems. An accompanying website with Quartus II software enables readers to replicate the book's examples and perform the exercises.

This book can be used for either a two- or one-semester course for undergraduate students in electrical and computer engineering and computer science. Its thorough explanation of theory, coupled with examples and exercises, enables both students and practitioners to master and implement modern digital design techniques with confidence.

Table of contents provided by Syndetics

• Preface (p. xiii)
• 1 Number Systems and Binary Codes (p. 1)
• 1.1 Introduction (p. 1)
• 1.2 Decimal Numbers (p. 1)
• 1.3 Binary Numbers (p. 2)
• 1.3.1 Basic Binary Arithmetic (p. 5)
• 1.4 Octal Numbers (p. 8)
• 1.5 Hexadecimal Numbers (p. 11)
• 1.6 Signed Numbers (p. 13)
• 1.6.1 Diminished Radix Complement (p. 14)
• 1.6.2 Radix Complement (p. 16)
• 1.7 Floating-Point Numbers (p. 19)
• 1.8 Binary Encoding (p. 20)
• 1.8.1 Weighted Codes (p. 20)
• 1.8.2 Nonweighted Codes (p. 22)
• Exercises (p. 25)
• 2 Fundamental Concepts of Digital Logic (p. 29)
• 2.1 Introduction (p. 29)
• 2.2 Sets (p. 29)
• 2.3 Relations (p. 32)
• 2.4 Partitions (p. 34)
• 2.5 Graphs (p. 35)
• 2.6 Boolean Algebra (p. 37)
• 2.7 Boolean Functions (p. 41)
• 2.8 Derivation and Classification of Boolean Functions (p. 43)
• 2.9 Canonical Forms of Boolean Functions (p. 45)
• 2.10 Logic Gates (p. 48)
• Exercises (p. 53)
• 3 Combinational Logic Design (p. 59)
• 3.1 Introduction (p. 59)
• 3.2 Minimization of Boolean Expressions (p. 60)
• 3.3 Karnaugh Maps (p. 63)
• 3.3.1 Don't Care Conditions (p. 68)
• 3.3.2 The Complementary Approach (p. 70)
• 3.4 Quine-McCluskey Method (p. 73)
• 3.4.1 Simplification of Boolean Function with Don't Cares (p. 78)
• 3.5 Cubical Representation of Boolean Functions (p. 79)
• 3.5.1 Tautology (p. 82)
• 3.5.2 Complementation Using Shannon's Expansion (p. 84)
• 3.6 Heuristic Minimization of Logic Circuits (p. 85)
• 3.6.1 Expand (p. 85)
• 3.6.2 Reduce (p. 88)
• 3.6.3 Irredundant (p. 90)
• 3.6.4 Espresso (p. 92)
• 3.7 Minimization of Multiple-Output Functions (p. 95)
• 3.8 NAND-NAND and NOR-NOR Logic (p. 98)
• 3.8.1 NAND-NAND Logic (p. 98)
• 3.8.2 NOR-NOR Logic (p. 101)
• 3.9 Multilevel Logic Design (p. 102)
• 3.9.1 Algebraic and Boolean Division (p. 105)
• 3.9.2 Kernels (p. 106)
• 3.10 Minimization of Multilevel Circuits Using Don't Cares (p. 109)
• 3.10.1 Satisfiability Don't Cares (p. 110)
• 3.10.2 Observability Don't Cares (p. 112)
• 3.11 Combinational Logic Implementation Using EX-OR and AND Gates (p. 114)
• 3.12 Logic Circuit Design Using Multiplexers and Decoders (p. 117)
• 3.12.1 Multiplexers (p. 117)
• 3.12.2 Demultiplexers and Decoders (p. 123)
• 3.13 Arithmetic Circuits (p. 125)
• 3.13.1 Half-Adders (p. 125)
• 3.13.2 Full Adders (p. 126)
• 3.13.3 Carry-Lookahead Adders (p. 129)
• 3.13.4 Carry-Select Adder (p. 130)
• 3.13.5 Carry-Save Addition (p. 130)
• 3.13.6 BCD Adders (p. 132)
• 3.13.7 Half-Subtractors (p. 133)
• 3.13.8 Full Subtractors (p. 135)
• 3.13.9 Two's Complement Subtractors (p. 135)
• 3.13.10 BCD Substractors (p. 137)
• 3.13.11 Multiplication (p. 138)
• 3.13.12 Comparator (p. 140)
• 3.14 Combinational Circuit Design Using PLDs (p. 141)
• 3.14.1 PROM (p. 142)
• 3.14.2 PLA (p. 144)
• 3.14.3 PAL (p. 146)
• Exercises (p. 150)
• References (p. 155)
• 4 Fundamentals of Synchronous Sequential Circuits (p. 157)
• 4.1 Introduction (p. 157)
• 4.2 Synchronous and Asynchronous Operation (p. 158)
• 4.3 Latches (p. 159)
• 4.4 Flip-Flops (p. 162)
• 4.4.1 D Flip-Flop (p. 163)
• 4.4.2 JK Flip-Flop (p. 165)
• 4.4.3 T Flip-Flop (p. 167)
• 4.5 Timing in Synchronous Sequential Circuits (p. 168)
• 4.6 State Tables and State Diagrams (p. 170)
• 4.7 Mealy and Moore Models (p. 172)
• 4.8 Analysis of Synchronous Sequential Circuits (p. 175)
• Exercises (p. 177)
• References (p. 180)
• 5 VHDL in Digital Design (p. 181)
• 5.1 Introduction (p. 181)
• 5.2 Entity and Architecture (p. 182)
• 5.2.1 Entity (p. 182)
• 5.2.2 Architecture (p. 184)
• 5.3 Lexical Elements in VHDL (p. 185)
• 5.4 Data Types (p. 187)
• 5.5 Operators (p. 189)
• 5.6 Concurrent and Sequential Statements (p. 192)
• 5.7 Architecture Description (p. 194)
• 5.8 Structural Description (p. 196)
• 5.9 Behavioral Description (p. 199)
• 5.10 RTL Description (p. 200)
• Exercises (p. 202)
• 6 Combinational Logic Design Using VHDL (p. 205)
• 6.1 Introduction (p. 205)
• 6.2 Concurrent Assignment Statements (p. 206)
• 6.2.1 Direct Signal Assignment (p. 206)
• 6.2.2 Conditional Signal Assignment (p. 207)
• 6.2.3 Selected Conditional Signal Assignment (p. 211)
• 6.3 Sequential Assignment Statements (p. 214)
• 6.3.1 Process (p. 214)
• 6.3.2 If-Then Statement (p. 216)
• 6.3.3 Case Statement (p. 220)
• 6.3.4 If Versus Case Statements (p. 223)
• 6.4 Loops (p. 225)
• 6.4.1 For Loop (p. 225)
• 6.4.2 While Loop (p. 229)
• 6.5 For-Generate statement (p. 230)
• Exercises (p. 233)
• 7 Synchronous Sequential Circuit Design (p. 235)
• 7.1 Introduction (p. 235)
• 7.2 Problem Specification (p. 236)
• 7.3 State Minimization (p. 239)
• 7.3.1 Partitioning Approach (p. 239)
• 7.3.2 Implication Table (p. 242)
• 7.4 Minimization of Incompletely Specified Sequential Circuits (p. 244)
• 7.5 Derivation of Flip-Flop Next State Expressions (p. 249)
• 7.6 State Assignment (p. 257)
• 7.6.1 State Assignment Based on Decomposition (p. 261)
• 7.6.2 Fan-out and Fan-in Oriented State Assignment Techniques (p. 265)
• 7.6.3 State Assignment Based on 1-Hot Code (p. 271)
• 7.6.4 State Assignment Using m-out-of-n Code (p. 271)
• 7.7 Sequential PAL Devices (p. 273)
• Exercises (p. 286)
• References (p. 290)
• 8 Counter Design (p. 291)
• 8.1 Introduction (p. 291)
• 8.2 Ripple (Asynchronous) Counters (p. 291)
• 8.3 Asynchronous Up-Down Counters (p. 294)
• 8.4 Synchronous Counters (p. 295)
• 8.5 Gray Code Counters (p. 300)
• 8.6 Shift Register Counters (p. 302)
• 8.7 Ring Counters (p. 307)
• 8.8 Johnson Counters (p. 310)
• Exercises (p. 313)
• References (p. 313)
• 9 Sequential Circuit Design Using VHDL (p. 315)
• 9.1 Introduction (p. 315)
• 9.2 D Latch (p. 315)
• 9.3 Flip-Flops and Registers (p. 316)
• 9.3.1 D Flip-Flop (p. 316)
• 9.3.2 T and JK Flip-Flops (p. 318)
• 9.3.3 Synchronous and Asynchronous Reset (p. 320)
• 9.3.4 Synchronous and Asynchronous Preset (p. 322)
• 9.3.5 Registers (p. 322)
• 9.4 Shift Registers (p. 324)
• 9.4.1 Bidirectional Shift Register (p. 326)
• 9.4.2 Universal Shift Register (p. 327)
• 9.4.3 Barrel Shifter (p. 327)
• 9.4.4 Linear Feedback Shift Registers (p. 329)
• 9.5 Counters (p. 332)
• 9.5.1 Decade Counter (p. 334)
• 9.5.2 Gray Code Counter (p. 335)
• 9.5.3 Ring Counter (p. 336)
• 9.5.4 Johnson Counter (p. 337)
• 9.6 State Machines (p. 338)
• 9.6.1 Moore-Type State Machines (p. 338)
• 9.6.2 Mealy-Type State Machines (p. 341)
• 9.6.3 VHDL Codes for State Machines Using Enumerated Types (p. 342)
• 9.6.4 Mealy Machine in VHDL (p. 345)
• 9.6.5 User-Defined State Encoding (p. 351)
• 9.6.6 1-Hot Encoding (p. 355)
• 9.7 Case Studies (p. 356)
• Exercises (p. 368)
• References (p. 371)
• 10 Asynchronous Sequential Circuits (p. 373)
• 10.1 Introduction (p. 373)
• 10.2 Flow Table (p. 374)
• 10.3 Reduction of Primitive How Tables (p. 377)
• 10.4 State Assignment (p. 379)
• 10.4.1 Races and Cycles (p. 379)
• 10.4.2 Critical Race-Free State Assignment (p. 381)
• 10.5 Excitation and Output Functions (p. 387)
• 10.6 Hazards (p. 390)
• 10.6.1 Function Hazards (p. 391)
• 10.6.2 Logic Hazards (p. 393)
• 10.6.3 Essential Hazards (p. 396)
• Exercises (p. 398)
• References (p. 401)
• Appendix CMOS Logic (p. 403)
• A.1 Transmission Gates (p. 405)
• A.2 Clocked CMOS Circuits (p. 407)
• A.3 CMOS Domino Logic (p. 408)
• Index (p. 411)

Author notes provided by Syndetics