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Low cost flip chip technologies : for DCA, WLCSP, and PBGA assemblies / John H. Lau.

By: Lau, John H.
Material type: materialTypeLabelBookPublisher: New York ; London : McGraw-Hill, 2000Description: xxii, 585 p. : ill. ; 24 cm. + hbk.ISBN: 0071351418.Subject(s): Multichip modules (Microelectronics) -- Design and construction | Microelectronic packagingDDC classification: 621.3815
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Enhanced descriptions from Syndetics:

Low-Cost Flip Chip Technologies:For DCA, WLCSP, and PBGA AssembliesJohn H. LauThe first comprehensive and in-depth guide to low-cost flip chip technologies, this reference gives you cutting edge information on the most important new developments and latest research results in applying flip chip technologies to direct chip attach (DCA) - also called flip chip on board (FCOB), wafer level chip scale package (WLCSP), and plastic ball grid array (PBGA) package assemblies. For professionals active in flip chip research and development, those who wish to master flip chip problem-solving methods, and those who must choose a cost-effective design and high-yield manufacturing process for their interconnect systems, here is a timely summary of progress in all aspects of this fascinating field.This one-stop guide meets the reference needs of engineers in the fields of design, materials, process, equipment, manufacturing, quality control, product assurance, reliability, component, packaging, marketing, and systems design, and technical managers working in electronic packaging and interconnection. With this book you will develop a practical understanding of the economic, design, materials, process, equipment, quality, manufacturing, and reliability issues of low-cost flip chip technologies. Among the topics explored:· IC trends and packaging technology updates· More than 12 different wafer-bumping methods· More than 100 lead-free solder alloys· Sequential build up PCB with microvias and via-in-pad· FCOB with anisotropic conductive film (ACF)· FCOB with anisotropic conductive adhesive (ACA)· Solder-bumped FCOB with conventional underfills· Solder-bumped FCOB with no-flow underfills· Solder-bumped FCOB with imperfect underfills· Physical and mechanical properties of underfills· How to select underfill materials· Thermal management of solder-bumped FCOB· Reliability of solder-bumped FCOB· Failure analysis of solder-bumped FCOB· Design, materials, process, and reliability of WLCSPs· Solder-bumped flip chip in PBGA packages· Fracture mechanics analysis of delaminations· Creep analysis of solder jointsLow-cost flip chip technology is taking the electronics industry by storm. Page after page, this standard-setting guide gives you both essential technical details and an eye-opening overview of this fast-developing field. No matter how you use Low-Cost Flip Chip Technologies For DCA, WLCSP, and PBGA Assemblies, you'll see why it's the resource of choice for those who want to be at the top of the game.

Includes bibliographical references and index.

Table of contents provided by Syndetics

  • Foreword (p. xv)
  • Preface (p. xvii)
  • Acknowledgments (p. xxi)
  • Chapter 1. Integrated Circuit Packaging Trends (p. 1)
  • 1.1 Introduction (p. 1)
  • 1.2 IC Trends (p. 2)
  • 1.2.1 IC Density and Feature Size (p. 2)
  • 1.2.2 IC Operating Voltage (p. 3)
  • 1.2.3 Microprocessor, ASIC, DRAM, and SRAM (p. 4)
  • 1.2.4 Copper Interconnects (p. 6)
  • 1.2.5 Moore's Law (p. 8)
  • 1.3 Packaging Technology Update (p. 9)
  • 1.3.1 Area-Array Flip Chip Technology (p. 11)
  • 1.3.2 BGA Technology (p. 12)
  • 1.3.3 TCP (p. 12)
  • 1.3.4 TSOP and PQFP (p. 12)
  • 1.3.5 CSP and DCA (p. 13)
  • 1.3.6 Wafer-Level Packaging (p. 13)
  • 1.4 Summary (p. 16)
  • References (p. 17)
  • Chapter 2. Chip-Level Interconnects: Wire Bonds and Solder Bumps (p. 27)
  • 2.1 Introduction (p. 27)
  • 2.2 Wire Bonds Versus Solder Bumps (p. 28)
  • 2.2.1 Assembly Process (p. 33)
  • 2.2.2 Major Equipment (p. 34)
  • 2.2.3 Cost of Materials (p. 35)
  • 2.2.4 Summary (p. 43)
  • 2.3 Wafer Bumping with Solders (p. 43)
  • 2.3.1 Evaporation Method (p. 44)
  • 2.3.2 Electroplating Method (p. 47)
  • 2.3.3 Under-Bump Metallurgy (UBM) (p. 48)
  • 2.3.4 Stencil Printing Method (p. 50)
  • 2.3.5 Solder Jet Printing Method (p. 55)
  • 2.3.6 Fly-Through Solder Jet Printing Method (p. 58)
  • 2.3.7 Micropunching Method (p. 61)
  • 2.3.8 Molten Solder Injection Method (p. 67)
  • 2.3.9 SuperSolder Method (p. 69)
  • 2.3.10 Microball Mounting Method (p. 72)
  • 2.3.11 Tacky Dots Method (p. 78)
  • 2.3.12 Solder Bumps on PCB Method (p. 84)
  • 2.3.13 Solder Bumps on AI Pads Without UBM (p. 84)
  • 2.4 Alpha Particle (p. 89)
  • 2.5 Wafer Bumping with Solderless Materials (p. 90)
  • Acknowledgments (p. 90)
  • References (p. 90)
  • Chapter 3. Lead-Free Solders (p. 95)
  • 3.1 Introduction (p. 95)
  • 3.2 Worldwide Efforts on Lead-Free Solders (p. 95)
  • 3.3 Physical and Mechanical Properties of Lead-Free Solders (p. 100)
  • 3.3.1 Determining Melting Temperature with a DSC (p. 100)
  • 3.3.2 Determining TCE with TMA (p. 103)
  • 3.3.3 Measuring Storage Modulus with DMA (p. 105)
  • 3.3.4 Measuring Moisture Absorption with TGA (p. 109)
  • 3.3.5 Steady-State Creep of Lead-Free Solders (p. 110)
  • 3.3.6 Isothermal Fatigue of Lead-Free Solders (p. 114)
  • 3.3.7 Thermal Fatigue of Lead-Free Solders (p. 115)
  • 3.4 Lead-Free Solders for Flip Chip Applications (p. 116)
  • 3.4.1 Melting Characteristics (p. 116)
  • 3.4.2 Electrical Resistivity (p. 116)
  • 3.4.3 Wetability (p. 118)
  • 3.4.4 Microhardness (p. 118)
  • Acknowledgments (p. 118)
  • References (p. 119)
  • Chapter 4. High-Density PCB and Substrates (p. 121)
  • 4.1 Introduction (p. 121)
  • 4.2 Categories of Vias (p. 122)
  • 4.3 Forming Microvias by Conventional Mechanical NC Drilling (p. 125)
  • 4.4 Forming Microvias by Laser Drilling (p. 126)
  • 4.4.1 Materials Choice with Laser Drilling (p. 127)
  • 4.4.2 CO[subscript 2] Laser (p. 128)
  • 4.4.3 UV-YAG Laser (p. 128)
  • 4.4.4 Excimer Laser (p. 130)
  • 4.4.5 Comparison of Excimer, UV-YAG, and CO[subscript 2] Lasers (p. 130)
  • 4.5 Photo-Defined Microvias (p. 132)
  • 4.5.1 Process for Photo-Defined Vias (p. 132)
  • 4.5.2 Notes on Photo-Defined Vias (p. 133)
  • 4.5.3 Materials Choice with Photo-Defined Vias (p. 133)
  • 4.5.4 Design Guidelines and Equipment with Photo-Defined Vias (p. 134)
  • 4.5.5 Reliability Data with Photo-Defined Vias (p. 134)
  • 4.6 Chemical (Wet)- and Plasma (Dry)-Etched Microvias (p. 135)
  • 4.6.1 Process for Etched Vias (p. 135)
  • 4.6.2 Notes on Plasma-Etched Vias (p. 136)
  • 4.7 Conductive-Ink-Formed Microvias (p. 136)
  • 4.7.1 Materials Choice (p. 138)
  • 4.7.2 Fabrication Process of CB100 (p. 138)
  • 4.7.3 Fabrication Process of ALIVH (p. 140)
  • 4.7.4 Reliability of Conductive-Ink-Formed Vias (p. 140)
  • 4.8 Microvia Production in Japan (p. 141)
  • 4.8.1 Fujitsu Limited (p. 141)
  • 4.8.2 Hitachi Chemical Co. (p. 142)
  • 4.8.3 Ibiden (p. 142)
  • 4.8.4 IBM at Yasu (p. 142)
  • 4.8.5 JVC (p. 142)
  • 4.8.6 Matsushita (p. 143)
  • 4.8.7 NEC (p. 143)
  • 4.8.8 Toshiba (p. 143)
  • 4.8.9 Summary (p. 143)
  • 4.9 Micro Via-in-Pad (VIP) (p. 145)
  • 4.10 Useful Design Charts for High-Speed Circuits (p. 145)
  • Acknowledgments (p. 154)
  • References (p. 154)
  • Chapter 5. Flip Chip on Board with Solderless Materials (p. 157)
  • 5.1 Introduction (p. 157)
  • 5.2 FCOB Assemblies with ACF (p. 157)
  • 5.2.1 The Wafer (p. 158)
  • 5.2.2 Wafer Bumping with Au, Cu, and Ni-Au (p. 159)
  • 5.2.3 PCB (p. 163)
  • 5.2.4 ACF (p. 164)
  • 5.2.5 FCOB Assembly with ACF (p. 165)
  • 5.2.6 Thermal Cycling Test of FCOB Assemblies with ACF (p. 170)
  • 5.2.7 SIR Test Results of FCOB Assemblies with ACF (p. 172)
  • 5.2.8 Summary (p. 172)
  • 5.3 FCOB Assemblies with ACA (p. 173)
  • 5.3.1 IC, PCB, and ACA Materials (p. 174)
  • 5.3.2 FCOB with Ni-Au Bumps and ACA (p. 175)
  • 5.3.3 FCOB with Au Bumps and ACA (p. 178)
  • 5.3.4 Accelerated Aging Test and Results (p. 178)
  • 5.3.5 Summary (p. 179)
  • Acknowledgments (p. 181)
  • References (p. 181)
  • Chapter 6. Flip Chip on Board with Conventional Underfills (p. 183)
  • 6.1 Introduction (p. 183)
  • 6.2 FCOB with High-Temperature Solder Bumps (p. 184)
  • 6.3 FCOB with Low-Temperature Solder Bumps (p. 186)
  • 6.4 Most Desirable Features of Underfills (p. 189)
  • 6.5 Handling and Application of Underfills (p. 190)
  • 6.6 Curing Conditions of Underfills (p. 191)
  • 6.7 Material Properties of Underfills (p. 193)
  • 6.7.1 TCE (p. 193)
  • 6.7.2 Storage Modulus (p. 194)
  • 6.7.3 Tan [delta] and T[subscript g] (p. 195)
  • 6.7.4 Moisture Content (p. 196)
  • 6.7.5 Young's Modulus (p. 197)
  • 6.7.6 Stress-Strain Relations (p. 199)
  • 6.7.7 Creep Curves (p. 200)
  • 6.7.8 Fracture Toughness of Underfills (p. 201)
  • 6.7.9 Fracture Toughness of Underfill-Chip Interfaces (p. 202)
  • 6.7.10 Fracture Toughness of Underfill-PCB Interfaces (p. 204)
  • 6.8 Flow Rate of FCOB with Underfills (p. 204)
  • 6.9 Shear Test of FCOB with Underfills (p. 206)
  • 6.9.1 Test Results (p. 206)
  • 6.9.2 Failure Modes (p. 206)
  • Acknowledgments (p. 210)
  • References (p. 210)
  • Chapter 7. Flip Chip on Board with No-Flow Underfills (p. 223)
  • 7.1 Introduction (p. 223)
  • 7.2 No-Flow Liquidlike Underfill Materials (p. 224)
  • 7.3 Curing Conditions of Liquidlike Underfills (p. 227)
  • 7.4 Material Properties of Liquidlike Underfills (p. 232)
  • 7.4.1 TCE (p. 232)
  • 7.4.2 Storage Modulus and Loss Modulus (p. 233)
  • 7.4.3 T[subscript g] (p. 233)
  • 7.4.4 Moisture Content (p. 234)
  • 7.5 FCOB Assembly with Liquidlike No-Flow Underfills (p. 237)
  • 7.6 Reliability Testing of FCOB with Liquidlike No-Flow Underfills (p. 240)
  • 7.6.1 Shear Test (p. 240)
  • 7.6.2 Thermal Cycling Test (p. 240)
  • 7.7 Nonlinear Finite Element Analysis of Liquidlike Underfills (p. 241)
  • 7.8 Summary and Recommendations for Liquidlike Underfills (p. 246)
  • 7.9 FCOB with Filmlike No-Flow Underfills (p. 251)
  • 7.9.1 Material (p. 251)
  • 7.9.2 Process (p. 251)
  • 7.9.3 Shear Test (p. 252)
  • 7.9.4 Summary and Recommendations (p. 253)
  • Acknowledgments (p. 256)
  • References (p. 256)
  • Chapter 8. Flip Chip on Board with Imperfect Underfills (p. 263)
  • 8.1 Introduction (p. 263)
  • 8.2 Possible Failure Modes of FCOB with Imperfect Underfills (p. 264)
  • 8.3 Fracture Mechanics in Finite Element Analysis (p. 265)
  • 8.4 FCOB with Imperfect Underfills near the Fillet Areas (p. 267)
  • 8.4.1 Problem Definition (p. 267)
  • 8.4.2 Effects of Imperfect Fillet Underfills on Solder Joint Reliability (p. 271)
  • 8.5 FCOB with Imperfect Underfills near the Corner Solder Joints (Chip Size Effect) (p. 277)
  • 8.5.1 Problem Definition (p. 277)
  • 8.5.2 Effects of Chip Size on Solder Joint Reliability Without Underfill (p. 278)
  • 8.5.3 Effects of Chip Size on Solder Joint Reliability with Perfect Underfill (p. 280)
  • 8.5.4 Effects of Chip Size on Solder Joint Reliability with Imperfect Underfill (p. 280)
  • 8.5.5 Summary (p. 282)
  • 8.6 FCOB with Imperfect Underfill near the Corner Solder Joints (PCB Thickness Effect) (p. 285)
  • 8.6.1 Problem Definition (p. 285)
  • 8.6.2 Stresses and Strains at the Corner Solder Joint (p. 285)
  • 8.6.3 Strain Energy Release Rate and Phase Angle at the Crack Tip (p. 289)
  • 8.6.4 Summary (p. 290)
  • 8.7 Effects of Underfill Voids on Solder Joint Reliability (p. 291)
  • 8.7.1 Problem Definition (p. 291)
  • 8.7.2 Stresses and Strains at the Corner Solder Joint (p. 292)
  • 8.7.3 Strain Energy Release Rate and Phase Angle at the Crack Tip (p. 294)
  • 8.7.4 Summary (p. 295)
  • Acknowledgments (p. 298)
  • References (p. 298)
  • Chapter 9. Thermal Management of Flip Chip on Board (p. 301)
  • 9.1 Introduction (p. 301)
  • 9.2 The SGS-Thomson Test Chip (p. 301)
  • 9.3 Effects of PCB Construction (p. 302)
  • 9.4 Effect of Air Flow (p. 303)
  • 9.5 Effects of Chip Size and Power Dissipation Area (p. 304)
  • 9.6 Heat Paths of Solder-Bumped Flip Chip on Board (p. 306)
  • 9.7 Effects of Solder Joint Population (p. 308)
  • 9.8 Effects of Signal Copper Content in PCB (p. 308)
  • 9.9 Effects of Underfill Materials (p. 309)
  • 9.10 Effects of Heat Sinks (p. 310)
  • 9.11 Summary (p. 312)
  • Acknowledgments (p. 314)
  • References (p. 314)
  • Chapter 10. Wafer-Level Packaging (p. 317)
  • 10.1 Introduction (p. 317)
  • 10.2 EPS/APTOS's WLCSP (p. 318)
  • 10.2.1 WLCSP Redistribution and Bumping (p. 318)
  • 10.2.2 WLCSP Solder Bump Height (p. 320)
  • 10.2.3 WLCSP Solder Bump Strength (p. 322)
  • 10.2.4 PCB Assembly of WLCSP (p. 322)
  • 10.2.5 Finite Element Modeling of WLCSP Assemblies (p. 323)
  • 10.2.6 Time-Temperature-Dependent Creep Analysis (p. 324)
  • 10.2.7 Life Prediction for WLCSP Corner Solder Joint (p. 329)
  • 10.2.8 Shear Test of WLCSP on Board (p. 330)
  • 10.2.9 Thermal Cycling of WLCSP on Board (p. 330)
  • 10.2.10 Summary (p. 330)
  • 10.3 Amkor/Anam's wsCSP (p. 331)
  • 10.3.1 wsCSP Design and Assembly Flow (p. 332)
  • 10.3.2 wsCSP Package-Level Reliability (p. 333)
  • 10.3.3 wsCSP on Board Reliability Tests (p. 336)
  • 10.3.4 Summary (p. 339)
  • 10.4 Hyundai's Omega-CSP (p. 339)
  • 10.4.1 Design of Omega-CSP (p. 339)
  • 10.4.2 Materials for Omega-CSP (p. 341)
  • 10.4.3 Processing of Omega-CSP (p. 341)
  • 10.4.4 Reliability of Omega-CSP on Board (p. 343)
  • 10.5 FormFactor's WLCSP (p. 344)
  • 10.5.1 MicroSpring (p. 344)
  • 10.5.2 MicroSpring Flip Chip on Board (p. 345)
  • 10.5.3 Reliability of MicroSpring Flip Chip on Board (p. 346)
  • 10.5.4 Applications of MicroSpring Flip Chip on Board (p. 346)
  • 10.6 Tessera's WAVE (p. 348)
  • 10.6.1 Uniqueness of WAVE (p. 348)
  • 10.6.2 Design of WAVE (p. 350)
  • 10.6.3 Processing of WAVE (p. 350)
  • 10.6.4 Reliability of WAVE (p. 352)
  • 10.6.5 WAVE's Solution to Die Shrink (p. 353)
  • 10.7 Oxford's WLCSP (p. 353)
  • 10.7.1 Device Design (p. 356)
  • 10.7.2 Device Fabrication (p. 356)
  • 10.7.3 Processing of WLCSP for Optoelectronic Devices (p. 357)
  • Acknowledgments (p. 359)
  • References (p. 359)
  • Chapter 11 Solder-Bumped Flip Chip on Micro Via-in-Pad Substrates (p. 363)
  • 11.1 Introduction (p. 363)
  • 11.2 Flip Chip on Micro-VIP Substrate in a CSP (p. 363)
  • 11.2.1 IC Wafer for the 32-Pin SRAM Device (p. 364)
  • 11.2.2 Micro-VIP Substrate (p. 365)
  • 11.2.3 Solder-Bumped Flip Chip on Micro-VIP Substrate (p. 367)
  • 11.2.4 PCB Assembly of the Micro-VIP CSP (p. 367)
  • 11.2.5 Elastoplastic Analysis of the Micro-VIP (p. 370)
  • 11.2.6 Solder Joint Reliability of the Micro-VIP CSP Assembly (p. 375)
  • 11.2.7 Summary (p. 379)
  • 11.3 Effects of Underfill on the Deformations of SLC Substrates (p. 380)
  • 11.3.1 Problem Definition (p. 380)
  • 11.3.2 Experimental Results: Fringe Patterns (p. 380)
  • 11.3.3 Global Deformation of Surface Laminar Layer (p. 382)
  • 11.3.4 Local Deformation: Photosensitive Dielectric Layer (p. 383)
  • 11.3.5 Local Deformation: Solder Mask (p. 383)
  • 11.3.6 Local Deformation: Microvia (p. 384)
  • 11.3.7 Summary (p. 385)
  • Acknowledgments (p. 385)
  • References (p. 386)
  • Chapter 12. PCB Manufacturing, Testing, and Assembly of RIMMs (p. 389)
  • 12.1 Introduction (p. 389)
  • 12.2 PCB Manufacturing and Testing of Rambus Modules (p. 392)
  • 12.2.1 Electrical Requirements of Rambus Modules (p. 392)
  • 12.2.2 Manufacturing of Rambus Modules (p. 392)
  • 12.2.3 Electrical Measurement of Rambus Modules (p. 396)
  • 12.2.4 Measurement Results (p. 398)
  • 12.2.5 Summary and Recommendations (p. 402)
  • 12.3 PCB Assembly of [mu]BGA on Rambus Modules (p. 403)
  • 12.3.1 Tessera's [mu]BGA Component (p. 403)
  • 12.3.2 Test Board (p. 404)
  • 12.3.3 Assembly Flow Chart (p. 405)
  • 12.3.4 Paste, Printing, and Pick and Place (p. 405)
  • 12.3.5 Solder Reflow (p. 406)
  • 12.3.6 Two-Sided Assembly Results (p. 408)
  • 12.3.7 Shear Test and Results (p. 410)
  • 12.3.8 Thermal Cycling Test and Results (p. 411)
  • 12.3.9 Finite Element Modeling and Results (p. 413)
  • 12.3.10 Summary (p. 415)
  • Acknowledgments (p. 415)
  • References (p. 415)
  • Chapter 13. Wire Bonding Chip (Face-Up) in PBGA Packages (p. 417)
  • 13.1 Introduction (p. 417)
  • 13.2 Measurements of Popcorning of PBGA Packages (p. 417)
  • 13.2.1 Electrical Resistance Strain Gauge Method (p. 418)
  • 13.2.2 Solder Reflow of Dried PBGAs (p. 423)
  • 13.2.3 Solder Reflow of Moistured PBGAs (p. 427)
  • 13.2.4 Summary (p. 433)
  • 13.3 Popcorning of PBGA Packages by Fracture Mechanics (p. 434)
  • 13.3.1 Crack Initiation due to Thermal Expansion Mismatch (p. 435)
  • 13.3.2 Popcorning due to Thermal Expansion Mismatch and Pressure (p. 437)
  • 13.3.3 Fracture Mechanics Methods (p. 438)
  • 13.3.4 Fracture Mechanics Results (p. 440)
  • 13.3.5 Crack Growth in the Middle of the Die Attach (p. 442)
  • 13.3.6 Crack Growth at the Interface Between the Solder Mask and Copper (p. 447)
  • 13.3.7 Summary and Recommendations (p. 451)
  • 13.4 PCB Assembly of PBGA with Large PQFP Directly on the Opposite Side (p. 452)
  • 13.4.1 PBGA and PQFP Components (p. 452)
  • 13.4.2 Test Board (p. 454)
  • 13.4.3 Assembly Flow Chart (p. 454)
  • 13.4.4 Paste, Printing, and Pick and Place (p. 456)
  • 13.4.5 Solder Reflow (p. 456)
  • 13.4.6 Two-Sided Assembly Results (p. 456)
  • 13.4.7 Thermal Cycling Test and Results (p. 462)
  • 13.4.8 Summary (p. 463)
  • Acknowledgments (p. 463)
  • References (p. 464)
  • Chapter 14. Wire Bonding Chip (Face-Down) in PBGA Packages (p. 465)
  • 14.1 Introduction (p. 465)
  • 14.2 NuBGA Design Concepts (p. 466)
  • 14.2.1 Programmable VDD/VSS SVCs and Microstripline and Coplanar Stripline Traces (p. 467)
  • 14.2.2 Programmable VDD/VSS SWA and Microstripline and Coplanar Stripline Traces (p. 469)
  • 14.3 NuBGA Design Examples (p. 471)
  • 14.3.1 Conventional PCB Design Rules and Processes (p. 471)
  • 14.3.2 Electrically and Thermally Enhanced Low-Cost Package (p. 471)
  • 14.4 NuBGA Package Family (p. 474)
  • 14.5 NuBGA Electrical Performance (p. 474)
  • 14.5.1 NuBGA Package Parasitic Parameters (p. 474)
  • 14.5.2 NuBGA Package SSO Noise (p. 477)
  • 14.6 NuBGA Thermal Performance (p. 478)
  • 14.6.1 Problem Definition (p. 479)
  • 14.6.2 Temperature Distribution (p. 480)
  • 14.6.3 Thermal Resistance (p. 486)
  • 14.6.4 Cooling Power (p. 486)
  • 14.6.5 Solder Ball Temperature (p. 487)
  • 14.7 NuBGA Solder Joint Reliability (p. 490)
  • 14.8 Summary of the Standard NuBGA Packages (p. 493)
  • 14.9 Thinner Substrate and Nonuniform Heat Spreader NuBGA (p. 494)
  • 14.10 Thermal Performance of the New NuBGA Package (p. 496)
  • 14.10.1 Temperature Distribution (p. 496)
  • 14.10.2 Thermal Resistance (p. 496)
  • 14.10.3 Cooling Power (p. 498)
  • 14.10.4 Wind Tunnel Experimental Analysis (p. 500)
  • 14.11 Solder Joint Reliability of the New NuBGA Package (p. 504)
  • 14.12 Electrical Performance of the New NuBGA Package (p. 505)
  • 14.12.1 Capacitance (p. 505)
  • 14.12.2 Inductance (p. 506)
  • 14.13 Summary of the New NuBGA Package (p. 508)
  • Acknowledgments (p. 508)
  • References (p. 508)
  • Chapter 15. Solder-Bumped Flip Chip in PBGA Packages (p. 511)
  • 15.1 Introduction (p. 511)
  • 15.2 Intel's OLGA Package Technology (p. 511)
  • 15.2.1 OLGA Package Design (p. 513)
  • 15.2.2 OLGA Wafer Bumping (p. 513)
  • 15.2.3 OLGA Substrate Technology (p. 514)
  • 15.2.4 OLGA Package Assembly (p. 514)
  • 15.2.5 OLGA Package Reliability (p. 518)
  • 15.3 Mitsubishi's FC-BGA Package (p. 519)
  • 15.3.1 Wafer Bumping (p. 521)
  • 15.3.2 Mitsubishi's SBU Substrate (p. 523)
  • 15.3.3 PC-BGA Assembly Process (p. 523)
  • 15.3.4 Thermal Management (p. 525)
  • 15.3.5 Electrical Performance (p. 527)
  • 15.3.6 Qualification Tests and Results (p. 528)
  • 15.4 IBM's FC-PBGA Package (p. 529)
  • 15.4.1 Problem Definition (p. 529)
  • 15.4.2 CFD Analysis for Thermal Boundary Conditions (p. 530)
  • 15.4.3 Nonlinear Finite Element Stress Analysis (p. 531)
  • 15.4.4 Simulation Results (p. 534)
  • 15.4.5 Solder Joint Thermal Fatigue Life Prediction (p. 536)
  • 15.5 Motorola's FC-PBGA Packages (p. 537)
  • 15.5.1 Thermal Management of FC-PBGA Assemblies with E3 Bumps (p. 538)
  • 15.5.2 Solder Joint Reliability of FC-PBGA Assemblies with C4 Bumps (p. 544)
  • Acknowledgments (p. 545)
  • References (p. 547)
  • Chapter 16. Failure Analysis of Flip Chip on Low-Cost Substrates (p. 553)
  • 16.1 Introduction (p. 553)
  • 16.2 Failure Analysis of FCOB with Imperfect Underfills (p. 554)
  • 16.2.1 Test Chip (p. 554)
  • 16.2.2 Test Board (p. 556)
  • 16.2.3 Flip Chip Assembly (p. 556)
  • 16.2.4 Preconditions, Reflows, and Qualification Tests (p. 556)
  • 16.2.5 Failure Modes and Discussions (p. 557)
  • 16.2.6 Die Cracking (p. 562)
  • 16.2.7 Summary (p. 563)
  • 16.3 Interfacial Shear Strength (p. 566)
  • 16.3.1 Interfacial Shear Strength Between Solder Mask and Underfill (p. 566)
  • 16.3.2 Interfacial Shear Strength Between Passivation and Underfill (p. 567)
  • 16.3.3 Load Displacement Response of a Solder-Bumped FCOB Assembly (p. 568)
  • 16.3.4 Summary and Recommendations (p. 570)
  • Acknowledgments (p. 572)
  • References (p. 572)
  • Index (p. 575)

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